1. Field of the Invention
The present invention relates to a data access controller and data access control method, and particularly to a data access controller and data access control method which are intended for making access to the SRAM efficiently in the modulation/demodulation process, error detection/correction process, or data transfer process, for example.
2. Description of the Prior Art
In recording or playing back data to/from a recording medium such as a mini disc (MD) (trademark), it is necessary to prepare a static random access memory (SRAM) for each error correction code (ECC) block which is the unit of data recording and playback, and encode or decode an ECC block concurrently to the process of the modulator/demodulator (modem). On this account, it is a conceivable manner to have two or more SRAMS. In the following explanation, two SRAMs will be called a first SRAM and second SRAM.
At data recording, for example, data to be recorded is written into the first SRAM, the data is read out of the first SRAM by an ECC encoder, and the data, with C1 and C2 parities being appended thereto (will be termed "ECC block"), is written into the second SRAM. Concurrently with these operations, an ECC block is read out of the second SRAM by the modulator, and it is modulated and recorded on the MD.
At data playback, an ECC block is read out of the MD, and it is demodulated by the demodulator and written into the second SRAM. Concurrently to these operations, an ECC block is read out of the second SRAM, error detected and corrected by the ECC decoder, and written into the first SRAM.
Based on the provision of two SRAMs, it is possible to carry out concurrently the modulation/demodulation process by the modem and the encoding process by the ECC encoder or error detection/correction process by the ECC decoder.
However, the presence of two SRAMs results in an increased number of bus lines and a larger circuit scale. Moreover, the memory access time for external input/output is so tight that it is required for the external input/output operation to use another buffer SRAM, or reduce the number of times of performing the ECC detection/correction process, or raise the master clock frequency.